Long range ordered semiconductor interface phase and oxides

ABSTRACT

A semiconductor processing method capable of producing highly ordered, ultra thin dielectrics, including gate oxide and other semiconductor dielectrics, and interphase phases with low defect density. The process includes a degrease step, an etch, primary oxidation and then a passivation step which utilizes hydrofluoric acid to passivate the cleaned silicon surface with hydrogen. Dielectric layers may then be formed with low interface defect density, low flat band voltages and low fixed charge on semiconductor substrates.

The present application claims priority rights based on U.S. ProvisionalApplication Ser. No. 60/067,297, filed Nov. 28, 1997.

FIELD OF THE INVENTION

This invention relates to oxides grown on the surface of a substrate,more specifically to epitaxial oxides grown on the surface ofsemiconductors, and to the interface formed between the oxide and thesemiconductor.

BACKGROUND OF THE INVENTION

Ever since the first integrated circuit was demonstrated, one goal ofthe electronics industry has been to increase the density of individualdevices in an integrated circuit. The smaller the device, the faster theconduction across the device. Ultimately, as smaller devices are made,the devices can be packed more densely, which reduces transmissionbetween devices and also allows for faster operation.

Metal oxide semiconductor (MOS) technology forms the basis for a largepart of chip manufacturing. In typical MOS transistor technology, SiO₂is grown so as to form part of a metal oxide semiconductor gate. SiO₂ SOformed is commonly referred to as a gate oxide or a gate oxidedielectric. Until the time of this invention, SiO₂ grown on MOStransistor gates has always been thought of as amorphous with littleordering in the first atomic layers at the interface between the siliconsubstrate and the oxide layer.

When the semiconductor material is not silicon, i.e., it is one of themulti-element semiconductors (e.g. Si_(x)Ge_(1−x) or GaAs) or germanium,the growth of an oxide layer is problematic. For instance, amulti-element semiconductor containing Si, when exposed to oxidation,tends to form a silicon oxide material at the surface, but below thesilicon oxide layer the other material becomes more prevalent at theinterface since the silicon there is depleted by its reaction withoxygen to form the oxide. This creates defects and changes theelectrical characteristics of the interface.

Silicon has deficiencies as a semiconductor material when compared tosome multi-element semiconductor material. However, silicon is usedcommercially as a semiconductor preferentially over other materialsbecause it readily forms stable oxide dielectric layers with a lowerinterface defect density than other semiconductors and their oxides. Thestability of Si/SiO₂ having a low interface defect density enables themanufacture of transistors with better electrical properties than isattainable with other semiconductors.

The desire for lower dimension devices presents a basic problem: asdevices get smaller in three dimensions, the dielectric layer must getboth narrower and thinner and continue to function as a dielectric.Silicon does not always provide the optimum physical and electronicproperties, such as a low interface defect density or a high dielectricconstant, necessary to or tailored to fill a particular need. A desirefor materials that have better tailored physical and electronicproperties creates another problem: growth of dielectric layers onmulti-element semiconductors is difficult. These two problems becomeessentially insurmountable when one desires a small device made out of asemiconductor other than doped silicon. Conceptually, a solution wouldlie in producing either a well-ordered ultra-thin oxide on top of themulti-element semiconductor, or at least a more ordered interfacebetween the semiconductor and the dielectric layers. Doing so withoutelemental or phase separation is extremely difficult especially inchemical systems where the defect generation rate is higher thansilicon, and as the physical sizes involved approach atomic dimensions.Any improvement in ordering at the interface or in the material willimprove the interface defect density. It will be appreciated that, assmaller devices demand thinner dielectric layers, interfacecharacteristics become increasingly important.

Another goal of electronic device processing is the growth ofheterodielectrics or other materials listed below on a semiconductorsubstrate. While this goal is achievable for some systems, in general,growth of ordered films of a material on a semiconductor substrate isdifficult.

FIG. 1A shows a diagram depicting a gate structure, a commonconfiguration of components in a semiconductor device, in conjunctionwith an energy diagram 190. This diagram illustrates the relativeenergies for several critical parameters: the conduction band (E_(c)),the intrinsic Fermi level (E_(F,i)), the Fermi level (E_(f)) and thevalence band (E_(c)). In this figure SiO₂ (171) is exhibiting an idealinterface with silicon. The defect-free interface does not captureelectrons in the conduction path 175 of the p-type semiconductor 177.The energy diagram 190 clearly shows that the bands are flat for idealSiO₂.

FIG. 1B also depicts the arrangement as described in FIG. 1A. In thiscase, SiO₂ 179 has defects. These defects cause the bands to bend asseen in 192, for example electrons 181 (represented as minus signs)along the SiO₂/Si interface can be captured by these defects, thusdecreasing conduction in the n-channel 177.

In FIG. 1C, a voltage is applied to the gate structure 183. Though theSiO₂/Si interface 185 has defects, the applied voltage, V_(gate),attracts electrons at the SiO₂/Si interface 185, and fills the defects(also called electron traps) at the interface. Therefore, extraconduction electrons can then flow unhindered, furthermore the bands nowappear flat.

Disordered interface layers in the interfacial region, as discussedabove, bring forth several effects. Disorder increases the interfacedefect density which causes a change in the electronic structure of thebands at the interface; the bands bend. The bands in the material formfrom the overlap of each constituent atom's atomic orbitals. In adefect-free, non-molecular three dimensional solid, continuous bands canextend across the entire solid. In this case, a conduction band wouldprovide a continuous path across the material. See FIG. 1A.

Any defect, such as a dislocation or a point, line, or planar defect, inthe solid or at an interface, breaks the continuous nature of the bandsbecause the energy of electronic orbitals of atoms on one side of thedefect no longer align with the energy of orbitals of atoms on theother. This difference in alignment in the relative energies of theorbitals results in different energy levels for the overlappingorbitals. The energy levels of the continuous bands are defined by thedegree of local overlap between the atomic orbitals. When the defect isan elemental impurity, the situation is more complicated. Explainedsimplistically, the orbitals of the impurity atom occupy differentenergy levels which cause the electrons to occupy energy levels outsideof the bands. Because of the manner in which the atomic levels combineto form bands, the local perturbation in energy levels for dislocationsand impurity defects or any type of point, line or planar defects, asdescribed above, results in a local perturbation of the energy levelsinside or outside of the bands. Extra, discreet energy levels appearwhich can result in band bending. See FIG. 1B. Band bending, because itprovides additional energy levels in the conduction or the valencebands, can trap conduction electrons or holes. Electrical carriers arereferred to as trapped because, in addition to the electrical forcegenerated by the applied potential that causes conduction, an additionalpotential must also be applied to dislodge these trapped electrons andcause them to move.

To an extent, the interface between the dielectric layer on the surfaceof a semiconductor and the semiconductor itself acts like a defect.While it provides a discontinuity in the conduction band itself, theinterface, if not ideal or perfect, causes the conduction band in thesemiconductor material to be perturbed and therefore, produces bandbending. Defects in the dielectric near the interface can also perturbthe bands in the semiconductor. Band bending at the interface interfereswith the flow of conduction electrons in the region of the semiconductormaterial immediately below the interface. As devices made fromsemiconductors become smaller, the interference with conduction causedby band bending becomes more important as described below.

To enable the defect containing material to function as a semiconductor,the trapping caused by band bending must be overcome regardless ofwhether the defect is due to dislocations, impurities, or any point,line, or planar defects or due to a layer of dielectric on the surfaceand the interface it forms. To a large extent in semiconductormaterials, this is accomplished by producing very pure, highlycrystalline materials and ultraclean, impurity-free interfaces. However,those methods do not deal with band bending caused by the intrinsicdefect density of the interface between the dielectric and semiconductormaterial. Currently, this interface band bending is overcome by applyinga voltage known as the flat band voltage. This voltage realigns thebands back to a flat condition, exactly compensating for bandperturbations caused by any types of defects in the interfacial region.When the semiconductor material is part of a transistor, the flat-bandvoltage must be applied in addition to any control voltage used tooperate the transistor. See FIG. 1C. Therefore, a device with a poorerelectronic structure at the interface has a larger necessary biasvoltage and higher power consumption. The need for the application of alarger bias voltage in addition to the control voltage increases the netvoltage applied to the dielectric film. However, the thinner the film,the lower the voltage it can sustain. Thus, smaller transistordimensions require minimizing or decreasing this voltage so as not toexceed the breakdown voltage of the thin oxide. Furthermore, a higherdefect density at the interface results in more locations to pinconduction electrons, thereby decreasing the rate at which electrons cancross the device. The ideal interface structure has a low interfacedefect density, a low flat-band voltage, and a low fixed charge. Abetter, though heretofore unachieved, solution to band bending caused bythe interfacial region is to grow an interface that has a structurecommensurate with that of the semiconductor. The more the interfacialregion looks like the semiconductor, from the point of view of theatomic levels on the semiconductor atoms, the less band bending.Creating a gradual change in the nature of the structure in theinterfacial region causes less severe band bending. Another way toachieve this is to create an interface that has decreased interfacedefect density as compared to a conventional oxide. In other words, thegrowth of a more commensurate oxide or the formation of a morecommensurate interface region, independent of the bulk oxide phase,results in an improvement of the interface defect density and of theensuing electronic properties such as the flat band voltage, etc.

To minimize the interface defect density, considerable attention hasbeen given to the surface treatment of the crystalline semiconductorwafers from which chips are formed. A typical RCA clean consists ofdegreasing the surface of the wafer in an oxidizing, basic solution suchas 4-5:1:1 H₂O: H₂O₂: NH₄OH followed by an ionic clean/etch with a HFsolution. The use of this cleaning step is an attempt at improving thequality of the interface by removing first organic impurities, and thenmetallic impurities.

As the art of electronics is currently practiced, the use of smallerdimensions for devices in silicon and especially the use of smallerdevices for multi-element semiconductor materials is severely hamperedby the quality of dielectric layers that can be formed. Also, the growthof heterodielectics on semiconductor substrates is also very difficult.What is needed is a method for growing more ordered layers ofdielectrics and other material on the surfaces of semiconductors such asSi, Si_(x)Ge_(1−x), GaAs, Si_(1−x−y)Ge_(x)C_(y),Si_(3(1−x))Ge_(3x)N_(4(1−δ)), Ge, Si_(x)Ge_((1−x))(O_(y)N_(1−y))_(n),Si_(1−x−y)Ge_(x)C_(y)(O_(z)N_(1−z))_(n) and(Si_(1−x−y)Ge_(x)C_(y))₃N_(4−x−y), and GaAlAs. Another need is a methodthat will allow the growth of heterodielectrics and other materials suchas CaF₂, BaF₂, SrTiO₃, Pb(Zr,Ti)O₃, BaTiO₃, Zr(Ca)O₂, Zr(Y)O₂, LiNbO₃,(LiNbO₃, SrTiO₃), (Zr—Ca)O₂, Zr(Y)O₂), GaAs, Ga₂O₃, As₂O₅, CdTe, InP,ZnSe, ZnS, HgCdTe, GaSb, InSb, Yttrium Barium Copper Oxide, LanthanumStrontium Copper Oxide and Barium Europium Copper Oxide on the surfaceof a semiconductor substrate while substantially segregating thesubstrate from the overlayer.

SUMMARY OF THE INVENTION

In accordance with the invention, a method of producing ultra-thin filmsof a dielectric material on the surface of a substrate comprises thesteps of creating a clean, atomically smooth (thus planar) surface onthe substrate while simultaneously lowering the chemical reactivity ofthe surface so that any surface layer that forms naturally or is causedto form does so in a more ordered fashion than in conventional oxidesproducing a higher quality interface between the substrate surface andthe growing layer. One embodiment comprises the steps of degreasing thesurface of the substrate, then etching any native oxide off of thesurface of the substrate, reoxidizing the surface of the substrate, andetching while passivating the surface of the substrate. Optionally, afinal oxidation step can be employed. The invention consists of creatingan interface surface phase with low defect density, and optionally anoxide layer on top of it, either conventionally grown or ordered.

The invention also includes an interface phase and/or a dielectricmaterial produced using the above-mentioned method, a semiconductordevice having a dielectric produced using the above-mentioned method,and the dielectric composition of matter so-produced.

In one embodiment of the process, according to the invention, thesubstrate is prepared (either mechanically or chemically) to be verysmooth on the atomic level (one surface atomic step per 100-200 Å lineardistance, compared to one atomic step per 10-20 Å as is common in theart), while simultaneously removing the native oxide coating that existson virtually all substrates (element or alloy-like), removing mostorganic and metallic impurities, and then coating the surface of thesubstrate with an ultra-thin oxide-based dielectric or other surfacecoating which greatly retards the regrowth of the native oxide or otheroxygen containing surface species. The resulting slow film growth andthe extremely flat substrate surface combine synergistically to createan interface phase with an overlaid dielectric film comparable or betterin dielectric quality to the very best dielectric films preparedcommercially, but also much thinner and capable of being grown on mostmain group semiconductor substrates.

The dielectric layer thus-formed may be as thin as one half to ten nm.The process may include a preliminary degreasing step. An etching stepmay provide the smoothness and oxide and impurity removal. A primaryoxidation step and a passivation step may provide the ultra-thinoxide-based coating or interface phase. Optionally, a final oxidationstep may be employed. One of the main prerequisites in achieving anultra-thin film dielectric is beginning with a substrate surface that ispredominately smooth on the atomic level. Once the surface of thesubstrate is properly smoothed and passivated, then almost anywell-known oxidation method will produce a high quality dielectric layeron top of the interface phase because the preparation and passivationsteps promote slow growth of the oxide layer in well-known oxidationprocesses. In fact, if the surface is properly smoothed and cleaned, thepassivation step itself will result in an interface phase suitable foruse in microelectronic devices. The steps, called pre-passivation steps,of degreasing, etching, and primary oxidation create an atomicallysmooth, clean surface or a surface whose smoothness is improved ascompared to conventional processes. This yields an interface phase witha lower interface defect density.

When it is desired to form thicker dielectric layers, the finaloxidation step is employed. The prior surface preparation is stillnecessary even when a thicker layer is needed because the surfacepreparation seems to be the key factor in forming an interface phasethat is more ordered and has a lower interface defect density ascompared to conventional oxides. By making the surface smooth, thesurface preparation forms an appropriate foundation for an interfacethat has a low interface defect density with some degree of higher orderthan conventional oxides. This interface phase then can seed the growthof a suitable oxide layer of increased thickness.

In the case of a silicon containing substrate, when a final oxidationstep is not used, the surface prepared in accordance with the inventioncomprises an interface phase containing at least silicon, oxygen andhydrogen in an undetermined stoichiometry. When a final oxidation stepis used, the surface is substantially SiO₂. The final oxidation stepresults in an interface phase buried underneath an overlayer of SiO₂.However, the interface phase between the SiO₂ layer and the substrate isstill believed to comprise silicon, oxygen and hydrogen. Because theatomic structures of silicon-containing substrates and SiO₂ aredissimilar, the structure of the interface layer must bridge betweenthat of the silicon-containing substrate and that of SiO₂ by beingsubstantially compatible with the structure of the silicon substrate onone side and SiO₂ on the other. In making the transition between siliconand SiO₂, there will invariably be instances of empty oxygen and siliconvalence bonds. By the processes of this invention, it is believed that ahydrogen component serves to fill empty silicon or oxygen valence bondsat the interface. Furthermore, both infrared spectroscopy and ion beamanalysis indicate the presence of silicon, oxygen and hydrogen at theinterface. The actual bonding configuration of this interface phase hasan infrared spectroscopic signature that does not include siliconhydride absorptions.

Dielectric films of between one or two atomic layers to 20 nanometershave been grown on a substrate, specifically, the surface of Si(100).The thinnest films are grown at room temperature by exposure to ambientair after passivation (i.e. simple exposure to oxygen gas), or in thepassivation solution itself, or in a furnace at high temperature withlow oxygen flow and a high nitrogen flow, or at temperatures below theoxidation temperature for silicon below 850° C. Passivation slows therate of oxide formation, so that a higher quality interface phase forms.All well known commercial oxidation processes can function as the finaloxidation step in the practice of this invention including rapid thermaloxidation, furnace oxidation, high pressure oxidation and roomtemperature oxidation.

In connection with this invention, certain terms are used that arebelieved to be understood by those skilled in the art. “Long rangeordering” is an expression that means, in contradistinction to “shortrange ordering,” a regularity in the location of the atoms in astructure, such as a crystalline structure such that the location of anatom can be accurately predicted three, four, or more positions distantfrom a known atom location.

“Ultra-thin,” as used herein, means having a thickness of 40 Å or less.

“Interface defect density” is an expression used to mean a density ofsurface defects such atomic steps, missing atoms, or the presences ofunfilled bonds. “Low” interface density is interface density lower thanthat achieved in prior procedures, all other variables being equal.

By “low flat-band voltage” is meant a flat-band voltage lower than thatexperienced in devices prepared using conventional semiconductor wafercleaning and preparation, all other variables being equal.

“High capacitance” means a capacitance achieved that is higher than thatachieved by dielectrics using conventional semiconductor wafer cleaningand preparation, all other variables being equal.

The above and further advantages of this invention will be betterunderstood with reference to the following detailed description of thepreferred embodiments taken in combination with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagrammatic illustration of charge location and bandstructure of ideal SiO₂ deposited on a p-type semiconductor

FIG. 1B is a diagrammatic illustration of charge location and perturbedband structure of defects containing SiO₂ deposited on a p-typesemiconductor.

FIG. 1C is a diagrammatic illustration of charge location and aflat-band voltage compensated band structure of defect containing SiO₂deposited on a p-type semiconductor.

FIG. 2 is a diagrammatic illustration of a flow chart of steps in theprocess of forming dielectric layers in accordance with the presentinvention.

FIG. 3A is a diagrammatic illustration of a shadowing process in ionbeam analysis.

FIG. 3B is a diagrammatic illustration of channeling yield enhancementdue to minimal surface damage and the resultant disorder createdtherefrom from bombardment of ions during ion beam analysis. This sameview can represent a partially disordered surface before bombardment.

FIG. 3C is a diagrammatic illustration of channeling yield enhancementdue to extensive surface damage from bombardment of ions during ion beamanalysis. This view also represents a highly disordered surface beforebombardment.

FIG. 4 is a diagrammatic illustration of plot of oxygen areal densityversus ion dose in ion beam analysis.

FIG. 5A is a diagrammatic illustration of a MOS transistor structureshowing a prior art transistor.

FIG. 5B is a diagrammatic illustration of a MOS transistor structureshowing an embodiment of this invention wherein the interface phasefunctions as a gate oxide dielectric.

FIG. 5C is a diagrammatic illustration of a MOS transistor structureshowing an embodiment of this invention wherein the interface phase plusultra-thin dielectric film of the present invention function as a gateoxide dielectric.

FIG. 6A is a diagrammatic illustration of an electron micrograph showingunordered prior art semiconductor/dielectric interface.

FIG. 6B is a diagrammatic illustration of an electron micrograph showingthe ordered semiconductor/dielectric interface of the present invention.

DETAILED DESCRIPTION The Substrate

As used herein, the term “semiconductor” means any material that is notintrinsically a good conductor and that has a small enough band gap thatit could conceivably be doped to function as a semiconductor (i.e. aband gap that is less than approximately 10 eV) and that is chemicallyand otherwise compatible with the process of the invention.

Semiconductor substrates that should be suitable for use in theinvention include all group IV element and IV, IV—IV, and IV—IV—IVmulti-element substances, e.g. Si, Ge, Si_(x)Ge_(1−x), Si_(1−x−y)Ge_(x)C_(y), Ge_(x)C_(1−x), etc. When Ge is the substrate, thesolubility of the oxide may preclude use of the standard methoddisclosed below, but the broad process of creating a very smooth surfacealong with passivating the Ge surface will produce an ultra-thindielectric film. III-V semiconductors, e.g. GaAs, AlN, etc., are alsoexpected to be useful as substrate materials because of their highmobility and the ease of modulating their band gap. Nitride containingsemiconductors such as Si₃N₄ or Si_(3(1−x))Ge_(3x)N_(4(1−δ)) willfunction as substrates as well. Dielectrics on silicon and other groupIV, IV—IV, and IV—IV—IV materials such as nitrides and oxynitrides canbenefit from this method. These materials are both stable with respectto the solutions employed and can form a passivating hydrogen-basedlayer when exposed to a hydrogen source. They are also capable of beingetched by hydrofluoric acid (HF). II-VI semiconductors (ZnS or ZnSe)also benefit from very flat surface preparation and slow dielectricgrowth on the surface.

Surface Preparation

The steps in the process of the invention are illustrated in FIG. 2.Generally, all rinse steps may employ water or another solvent, asspecified, that can be deoxygenated or agitated by purging or bubblingwith N₂.

The first step 21 in the process is the degreasing step. This stepcleans loose contaminants from the surface of the substrate. It alsocompletely removes any organic impurities on the surface of thesubstrate, hence the term degreasing. The composition of the degreasingsolution is oxidizing and strongly basic. A preferred degreasingsolution contains 4 parts H₂O to 1 part 25-35% H₂O₂ solution and 1 partconc. NH₄OH solution measured by volume. However, a variety ofdegreasing solutions will suffice. The oxidizing agent and base shouldbe of high purity and lack metallic components. In successfulexperiments, the source of H₂O in the degreasing solution was highpurity DI H₂O of 18.3 megohm resistivity. The H₂O₂ and NH₄OH solutionswere of part per billion grade purity and certified as Class 10 cleanroom suitable. The invention was practiced with the degreasing solutionheld at 80° C. The substrate was retained in the degreasing solution forapproximately 10 minutes. The substrate was then rinsed in the DI H₂O asindicated at 31 in FIG. 2 for approximately 5 minutes. The DI H₂O usedin the rinse steps 31, 23, and 25 had been deoxygenated by purging withN₂ gas.

As indicated at 22 in FIG. 2, the next step is etching. This step isalso known as an ionic clean because it removes ionized impuritiesimbedded in the native oxide or located on the surface. It acts as acleaning step because it removes all oxide from the surface of thesubstrate and takes the surface down to the elemental (or multi-element)non-oxidized substrate by dissolving or etching away the surface oxidelayer. Any solution capable of dissolving the surface oxide andsolvating the ionic impurities would be suitable for use in the etchingstep 22. After etching, the substrate is again washed 23 with thedeionized water of 18.3 megohm resistivity.

A solution successfully used for etching has been a mixture of 98 partswater to 2 parts of 49% hydrofluoric acid solution measured by volume.The substrate was kept in the etching solution until such time that,when removed from the solution, it was not wetted by water. In otherwords, when all of the oxide layer has been removed, water will notadhere to the surface of the substrate (i.e., the surface has becomehydrophobic). This typically takes approximately 1 to 2 minutes in theexemplary etching solution described. The required time of immersion inthe etching solution depends upon the identity and concentration of theetching solution.

The next step 24 is reoxidation which has herein been designated the“primary” oxidation step. This step oxidizes the surface of thesubstrate. It also serves to further reduce ionic impurities. Anyimpurity left on the surface of the substrate is trapped in the oxidelayer that regrows during this step. Any solution capable of oxidizingthe surface of the substrate with an appropriate choice of treatmenttime and solution temperature is suitable for use in this invention.

In the actual practice of this invention, a solution of 4 parts H₂O to 1part 25-35% H₂O₂ solution to 1 part conc. HCl solution was employed. Thereagents were of part per billion grade purity and certified for use ina class 10 clean room. The solutions were held at 80 degrees C. in atemperature controlled water bath. The substrate was immersed in thisoxidation solution for approximately 10 minutes.

The goal of this step is to reoxidize the etched surface. Therefore, thetime and temperature of the actual practice of the invention is notconsidered critical. It is believed that the practice of the inventionwould be equally effective if the oxidizing solution were prepared inany of a wide range of concentrations, heated to any of a wide range oftemperatures and likewise for varying amounts of time, as long as afresh oxide layer was grown on the surface of the substrate. The oxidecould be grown by any thermal method of oxidation, such as thermalfurnace oxidation. This step is also followed by a rinse in deionizedwater, as described above and shown in 25.

Step 26 is the passivation step. In one embodiment of the invention, itis the final step in preparing the interface phase or the finaldielectric on the surface of the substrate. In another embodiment of theinvention, the passivation step is followed by a second oxidation,herein designated the “final” oxidation step.

The passivation step 26 removes the newly grown oxide layer and fillsany dangling or empty chemical valence bonds of the substrate surfacewith hydrogen, oxygen, or a mixture comprising oxygen and hydrogenbonded to Si. The layer grown in this step can retard the rate offurther oxide formation on the surface of the substrate. However, Si—Obond formation is not prevented and may take place in the passivationsolution. Ultimately, the goal is not to prevent oxide formation at thisstep, but to grow an ordered or a partially ordered interface phase or adielectric (even if it happens to not contain oxygen at all) with a lowinterface defect density. The interface phase or the dielectric thatforms upon removal from, and perhaps in, the passivation solution issuch a layer. This layer can be also be called a passivation layer.Furthermore, the surface of the substrate, once processed using theabove steps, provides a foundation that enables growth of thicker oxidelayers through additional oxidation steps while preserving a lowinterface defect density and a degree of order at the interface.

Any polar solvent capable of being easily removed and capable of forminga solution with a suitable etchant will function in this step. Thesolvent used in the passivation solution can be water, a non-alcoholicsolvent or an alcoholic solvent provided that it is capable of forming asolution with the etchant. In a preferred embodiment, the passivationsolution is prepared from an alcohol and 49% HF solution or H₂O and 49%HF solution. Any simple alcohol with a low enough volatility so that itcan be easily removed and that can form a solution with the etchant,will function as the alcohol portion of the passivation solution. Forexample, methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, and2-butanol are all expected to function in this invention. The treatmenttime for passivation should be chosen to be long enough to completelyremove the oxide layer formed in the prior oxidation step. In practice,that time ranges from about ½ to 5 minutes. The temperature of thepassivation solution can be varied. Note that higher temperatures couldcause a loss of alcohol and hydrofluoric acid as gases. In the actualpractice of this invention, the passivation solution was used at roomtemperature. Following the passivation step, the substrate is rinsed 27in deionized water or the solvent of the passivation step or anothersuitable solvent.

Optionally, after the passivation step 26 and rinse 27, a finaloxidation step 28 can be employed. All known oxidation processes areexpected to satisfactorily perform this final oxidation step. Oxidationmethods typically used in the semiconductor processing industry would beparticularly useful for the growth of thicker oxide films. These includerapid thermal oxidation, furnace oxidation, high pressure oxidation, androom temperature oxidation.

In actual, successful practice of the process, because metal impuritiesand contaminants can decrease the yield in semiconductor chipmanufacturing, non-metal containing reagents were used. Nevertheless, itis expected that the invention could be practiced with metal containingoxidizing agents, bases, or neutral agents.

The processes described will function under a wide range of purities ofreagents, temperatures of solutions, and times of treatment and rinses.The degreasing treatment time only has to be long enough to thoroughlyremove any organic surface contaminants. The degreasing solution can beat any temperature at which the solvent remains liquid. Lower purityreagents would cause a lower yield in any subsequent chip manufacturing,but would not detract from the bulk quality of the thin film as a whole.While lower purity reagents could potentially cause local qualityproblems in the film, it is likely that they could be used if steps weretaken to thoroughly rinse the substrate. At minimum, lower purityreagents can be used any time the desired end product could tolerate ahigher level of impurities in the film. On the other hand, increasingpurity decreases interface defect density and thus improves interfacequality.

In accordance with one aspect of the invention, there is employed atechnique for measuring oxygen, carbon and hydrogen coverage of thesubstrate with a precision better than 0.1 monolayers by ion beamanalysis (IBA) using a unique combination of conditions to obtaingreatly enhanced sensitivity. During IBA, ion channeling is combinedwith oxygen nuclear resonance at 3.05 MeV (¹⁶O(α,α)¹⁶O) in order toimprove the signal-to-noise ratio by a factor of up to 300. In addition,a direct measurement of crystal order becomes possible for the firsttime by comparing the total amount of oxygen measured from rotatingrandom spectra with the net amount of disordered oxygen measured bychanneling. Using this methodology, significant ordering overmacroscopic areas of thin film oxides has been observed. Direct ElectricRecoil Detection is used to measure hydrogen coverage.

A channeling measurement is done by directing an ion beam along aspecific direction or vector at the surface of the substrate. The oxygenatoms in the oxide surface layer shadow underlying oxygen atoms when theproper direction or vector is chosen. In a perfectly ordered oxide, themeasurement will detect surface oxygen and part of the shadowed oxygenatoms located in the region immediately adjacent to the surface. Theshadow of the oxygen surface atoms is called a shadow cone. The amountthat oxygen atoms further down from the surface contribute to themeasured oxygen depends on their depth. The deeper the oxygen atom isthe less it contributes to the detected signal, until a depth is reachedwhere the oxygen atoms no longer contribute at all. This depth-relateddecrease occurs, in part, because oxygen atoms deeper inside the solidare within the shadow cone of oxygen atoms closer to the surface, andthe cross-section of that shadow cone increases with depth, thusproviding a wider shadow. In FIG. 3A, the gray region 101 represents theshadow of a surface atom 103, as described above. Any portion of an atomwithin the shadow does not contribute to the signal measured duringchanneling. Atoms 105 are within the shadow 101, for example, and willnot be observed. In addition to oxygen atoms located near the surface,disordered oxygen is detected as well. When the ion beam is directedalong a particular vector, an atom that is crystallographically below anoxygen atom at the surface will not be detected because it is shadowed.Atoms 107 displaced from crystallographic positions are denoted bystripes. They are either unshadowed or not shadowed as completely ascrystallographically positioned atoms 105. While the channelingmeasurement measures ordered surface atoms plus a portion of thedisordered bulk, here the use of the term “disordered atoms” withrespect to IBA encompasses the value measured in the channelingmeasurement including disordered bulk atoms and ordered surface atoms.Comparing the channeled oxygen to the total oxygen measured by rotatingthe sample around the channeling vector yields a value proportional tothe amount of disordered oxygen. This ratio can be compared to otheroxides if both oxides have the same structure and the channeling vectoris the same. The lower the ratio of channeled oxygen to total oxygen inthis measurements, the higher the average order of the oxygen atoms inthe structure.

Oxygen atoms become displaced from their initial location during themeasurement when a particles (⁴He²⁺) impinge on the film because of thelow atomic number ratio of oxygen to ⁴He²⁺ (4:1) as compared to theatomic number ratio of Si to ⁴He²⁺ (7:1). A comparison between FIG. 3Aand FIG. 3B shows more atoms outside of the shadowed region after somebombardment. Eventually, after enough bombardment, the ordering isgreatly diminished. See FIG. 3C. Accompanying the decrease in orderingis an increase in the number of atoms outside of the shadowed region andtherefore an increase in the channeling yield. Oxygen and silicon yieldswere measured, not only for one fixed ⁴He²⁺ dose used for analysis, butalso as a function of successive doses, ranging from 10 to 50 times thedose necessary to accumulate enough statistics for one measurement. Themeasured oxygen yield versus ⁴He²⁺ dose is called a damage curve. SeeFIG. 4.

Structural damage resulting in atomic displacements can be observed in achanneling direction as the channeling yield gradually increases with⁴He²⁺ dose. However, the random yield is not affected. The random yieldmeasured via rotating random spectra depends on whether oxygen isdeposited or sputtered away during analysis. However, a steady, or inmost cases, slightly decreasing random yield has always been found foroxygen in the damage curves to date, while the channeling yield in caseswhere the oxide is very thin increases. The thinner the interface phaseformed, oxide or passivation layer, the more pronounced the damageeffect. The combination of these results removes any ambiguity; theoxygen atoms are progressively displaced by the analyzing probe, and theincrease in channeling yield cannot be attributed to an increase inoxide thickness, since the total amount of oxygen is either stable ordecreasing.

FIG. 4 shows an exemplary plot of channeling yield versus dose (numberof incident ⁴He²⁺ particles). As discussed above, the similarity betweenthe atomic masses of the ⁴He²⁺ particle and oxygen results in a fairamount of disruption of the ordered nature of the surface. Byextrapolating to zero dosage, the degree of ordering of the unbombardedsurface can be obtained. Hence, the channeling yield and the randomyield are always measured as the intercept of the damage curve with theoxygen yield axis, which corresponds to the initial oxygen yield priorto analysis. The curve is linear, as it is well known that the number ofatomic displacements scales linearly with ion dose at low dosages. Thisprocedure also has the advantage of decreasing the uncertainty on themeasured oxygen yield since it is based on a large set of IBAmeasurements. The typical error in the oxygen coverage is 2.0×10¹⁴atoms/cm² for channeling, and higher for the coverage measured viarotating random (7.3×10¹⁴ atoms/cm²) because of the lowersignal-to-noise ratio in individual rotating random spectra.

The normalized channeling yield, denoted as χ, is the ratio of thechanneling yield to random yield and scales with the degree of alignmentof oxygen with each other. As damage increases during analysis, atomscan be relocated inside the crystal lattice and the detection of theseatoms is thus enhanced. χ can then increase from below 1 to above 1, asobserved during an angular scan. In damage curves, this is seen when thechanneling yield, initially always lowest (χ<1) increases and in somecases reaches values above the random yield (χ>1).

Fourier transform infrared spectrophotometry in an attenuated totalreflectance mode (FTIR-ATR) was performed on a Nicolet Model 800 IRSpectrometer from Nicolet Instrument Corporation of Madison, Wisconsin.An accessory designed and manufactured by PIKE Technologies of Madison,Wisconsin used for FTIR-ATR holds whole Si wafers ranging in diameterfrom 100 to 200 mm without cutting the wafer or processing to create amultiple reflection element. The accessory provides good optical contactand reproducible clamping pressure, reducing fluctuations with appliedpressure, wafer curvature, and particulates in the instrument. Theexperiment uses π-polarized radiation and a 4 cm⁻¹ resolution. By usingπ-polarized radiation with a 60° Ge ATR (Attenuated Total Reflection)element, components perpendicular to the surface are preferentiallyexcited. The intensity enhancement obtained using π-polarization isapproximately a factor of 2.4 greater than unpolarized radiation. 256scans were signal-averaged to achieve a higher signal-to-noise ratio.Samples are referenced against a wafer chemically oxidized in a solutionprepared as described for 21 (i.e. 4:1:1 H₂O:H₂O₂: NH₄OH). Spectralanalysis is performed using the Omnic software of Nicolet InstrumentCorporation of Madison, Wis. Because the Ge crystal can be contaminatedor damaged over time and the difficulty of making reproducible contact,the best comparisons are obtained for FTIR performed on the same day.This caused (and always causes) the day-to-day IR absorptions for thesame peak to fall within a broader range than is seen in traditionalFTIR measurements. Measurements are averaged across the wafer diameter.For these measurements FTIR spectra were recorded within 24 hours ofchemical treatment.

Interface Phase/SiO₂-Overgrowth

The method disclosed herein first forms a very thin region upon whichthe thin film dielectric can be grown. This region is called theinterface phase. The interface phase because of its thinness isdifficult to characterize, but FTIR shows no evidence of Si-H bonding.The dielectric overlayer that grows on the interface phase is believedto be a separate phase from that of the interface phase because the twophases have different atomic densities.

Because SiO₂ is well-known to be a polymorphic material (multiple phaseswith the same stoichiometry), the interface phase and the ultra-thinSiO₂ grown thereon are believed to be polymorphic as well. As the phaseschange, the density and other mechanical properties of the materialschange as well. Control over the phases of ultra-thin SiO₂ and theinterface phase translates into control of density and, consequently,atomic positions within the phase. Ultimately, this measure of controlallows selection of mechanical properties (e.g. stress and warping),optical properties (e.g. refractive index) and electrical properties(e.g. dielectric constant). The capability of modulating these and otherproperties has tremendous implications for ultra-thin devices. Forexample, the paramount importance of increasing the dielectric constantas devices become smaller has been discussed above. The change inmechanical properties can be responsible for improving interface defectdensity; an improvement is observed even if the phase is not ordered,indicating that the change in mechanical properties (plasticity andelasticity) decreases stress locally and thus decreases defectgeneration.

The interface phase serves multiple roles, among those are its functionas a dielectric, as a seed layer, and as a barrier. The dielectricfunction has been discussed. When the phase acts as a seed layer, itdoes so by allowing atoms of the over-layer to arrange themselveswithout regard to the atomic arrangement of the substrate.

The interface phase acts as a barrier. When the interface phase forms,it segregates the semiconductor underneath from any heterodielectric orother material deposited on the surface. This segregation preventsreaction between the substrate and the overlayer and thereby preventscross contamination between the substrate and a deposited overlayer.Semiconductor substrates can include Si, Si_(x)Ge_(1−x), GaAs,Si_(1−x−y)Ge_(x)C_(y), Si_(3(1−x))Ge_(3x)N_(4(1−δ)), Ge,Si_(x)Ge_((1−x))(O_(y)N_(1−y))_(n),Si_(1−x−y)Ge_(x)C_(y)(O_(z)N_(1−z))_(n),(Si_(1−x−y)Ge_(x)C_(y))₃N_(4−x−y), and GaAlAs. Useful heterodielectricscan include CaF₂, BaF₂, SrTiO₃, Pb(ZrTi)O₃, BaTiO₃, Zr(Ca)O₂, Zr(Y)O₂,LiNbO₃, (LiNbO₃, SrTiO₃), (Zr—Ca)O₂, Zr(Y)O₂), GaAs, Ga₂O₃ As₂O₅, CdTe,InP, ZnSe, ZnS, HgCdTe, GaSb,InSb, Yttrium Barium Copper Oxide,Lanthanum Strontium Copper Oxide and Barium Europium Copper Oxide.

The SiO₂ based phases that form on the interface phase are at leastthree in number. The phases are classified based on their densityrelative to SiO₂. Type-A ultrathin SiO₂, ordered or not, has a densitysimilar to SiO₂. Type-B ultra-thin SiO₂, order or not, has a density upto 25-30% lower than SiO₂. Type-C ultra-thin SiO₂, again ordered or not,has a density greater than SiO₂. Thus, the thin film dielectricdiscussed herein can be one of at least three phases when SiO₂ is thechosen dielectric.

Any combinations of these ultra-thin SiO₂ phases produces a decrease inthe interface defect density. The term any combination encompasses mixedphases such as A_(1−x) B_(x),A_(1−x−y) B_(x) C_(y), A_(1−x) C_(x), etc.The improvement in interface defect density is expected to be evengreater when pure A, B or C ultra-thin SiO₂ phases are grown.

The state of the art measurements for evaluating interface qualityinclude measurement of trapped charge in the oxide, carrier lifetime,and capacitance. The state of the art values typically seen for SiO₂ onSi substrates are listed below. Note that the oxide layer is around 33 Åthick and that these measurements are dependent on thickness. Thetrapped charge seen commercially is between 8-20×10¹⁰ electrons/cm². Thevalues seen for dielectrics made by the process of this invention rangefrom 4-6.5×10¹⁰ electrons/cm² when measured on a thinner film. Thistranslates into values for the trapped charge for the interface phaseand overlaying dielectric that are on average at least twice as good ascommercially practiced. The carrier lifetime for charge carriers in thefilm of this invention are 1.5 to more than 2 times better thanconventionally prepared oxides. The capacitance is measured to be about10-30% higher for films 10-30% thinner. The capacitance measurementcorrelates directly with dielectric constant. The higher the capacitancevalue, the higher the quality of the dielectric. A thinner film shouldnot yield a higher capacitance unless the dielectric is of asignificantly higher quality.

The values listed above show that the ultra-thin film dielectrics of thepresent invention perform significantly better than those in commercialuse. This improvement is observed even though no ordering is observedbeyond the interface for the present dielectrics. Better ordereddielectric films will surpass the values listed above.

Device Manufacture

The process of this invention can be used to make a variety of differentsemiconductor devices including transistors, diodes, capacitors,resistors, memory, and charge-coupled devices. A transistor made usingthe process of this invention is illustrative.

In FIG. 5A, a field-effect transistor 50 has a source 52, a gate 54, anda drain 66. All of these portions are formed of the electrode metal andare well known in the art. Regions 58 and 62 are n-type and p-typesemiconducting material respectively. A layer 70 is a dielectricmaterial. Dielectric material layer 72 is the portion of the standardMOSFET that forms the gate-oxide dielectric. It is known in the art. InFIG. 5B, an ultra-thin gate-oxide dielectric 74 is a dielectric layerformed in the process of this invention. This film can be as thin as 0.5nm. In FIG. 5C, a thicker gate-oxide 76 is a dielectric layer formed inaccordance with the present invention including the final oxidation stepdescribed above. An interface layer 78 remains highly ordered with a lowinterface defect density after the thickness of the gate-oxide isincreased in the final oxidation.

The process of making integrated circuit transistors is well known inthe art. These processes employ layers of dielectric material in variousconfigurations depending on the nature of the device. The processdisclosed can be used to form those dielectric material layers.

EXAMPLES

Procedures that are common to each of the examples enumerated below aredescribed first. Following that description, each enumerated examplesets forth details specific to that experiment along with the relevantobserved data.

Semiconductor specimens were prepared in a chemical laminar flow hood,constructed of polypropylene, in a Class 100 clean room. The clean roomminimizes contamination of the samples. Unless otherwise specified,reagents were part per billion grade chemicals and were classified asClass 10 clean room suitable. Experiments on silicon used boron dopedsilicon(100) wafers, which had a resistivity of 10 to 14 ohm·cm. Twotypes of silicon specimens were used: 1) 1 by 1 inch pieces and 2) 100mm wafers. The 1 by 1 inch pieces were manually cut from a wafer using adiamond scribe in a Class 100 laminar flow hood located in the cleanroom. These were transferred between chemical treatments in apolytetrafluoroethylene (PTFE) carrier. At each step of the process,samples were stored in PTFE sample holders for characterization. The 1by 1 inch pieces were used for IBA.

The specimens were first treated with the degreasing solution at 80degrees C. for 10 minutes. This solution was held at 80 degrees C. in aborosilicate glass container which was heated by placing the glasscontainer in a polyvinyl butadiene tank filled with water. The water washeated by an immersion heater and was thermally regulated. Thedegreasing solution had a composition of 4:1:1 parts of H₂O:H₂O₂:NH₄OHby volume. After immersion in the degreasing solution, the specimenswere rinsed in 18.3 megohm resistivity DI H₂O for five minutes and driedwith N₂.

After the water rinse, the specimens were immersed in an etchingsolution for a period of time as specified below for each example. Theetching solution was held at room temperature and was prepared by mixing49% HF solution and H₂O at a ratio of 2:98 HF solution:H₂O. Followingthe etching solution, the specimens were again rinsed in 18.3 megohmresistivity DI H₂O for five minutes and dried with N₂.

Following the etching step, in a primary oxidation step, the surface ofeach specimen was oxidized in a solution held at 80° C. for ten minutesusing the same type water bath as described above with respect todegreasing. This reoxidizing solution was prepared as 4:1:1 H₂O: 25-40%H₂O₂: 25-40% Hcl solution. After the oxidation step, the specimens wereagain rinsed in DI H₂O and dried with N₂. Next, the process included thepassivation step. The above listed steps were repeated for each of thebelow listed examples unless otherwise specified. For a number of thespecimens, the passivation step ended the procedure. In general, in allrinse steps, whether the solvent was water or another solvent, thesolvent was deoxygenated by purging with N₂ gas.

As a comparative example, silicon (100) pieces etched in a solution of1:99 HF:H₂O were analyzed by IBA. The total amount of oxygen was8.3±1.2×10¹⁵ oxygen atoms/cm². Oxygen measured in the <111> directiongives a measurement of 3.9±0.32×10¹⁵ oxygen atoms/cm². Thus the averageunchanneled fraction in this case is about half: 0.47±0.05. Other thanetching, this example does not employ the pre-passivation steps beforethe passivation-type immersion step discussed.

As another comparative example, silicon (100) etched in a solution of1:9 HF:methanol gives a total oxygen coverage of 6.3±0.2×10¹⁵ oxygenatoms/cm². The <111> direction yields 4.2±0.6×10¹⁵ oxygen atoms/cm². Theaverage unchanneled fraction is high 0.68±0.14. Thus the ordering iseven lower and poorer when an isolated passivation step in alcohol isused rather than in water. Again, other than the etching, this exampledoes not employ the pre-passivation steps before the passivation-typeimmersion step.

Several operative examples are included below along with pertinentexperimental data in tabular form. The operative examples are followedby a discussion of the data. In each example the substrate was preparedas described above. The difference between the examples lies in thepassivation step as described below. All FTIR peaks are reported by theapproximate wavenumber of their absorption, note that FTIR-ATRabsorptions positions are typically not as reproducible day-to-day astraditional FTIR measurements.

Example 1 1:9 HF/methanol 1′-5′ rinse in DI H₂O

In this example, the passivation solution is 1:9 HF solution:methanol.After the pre-passivation steps were completed, the specimen(boron-doped Si(100) wafer) was immersed in the passivation solution forone minute. This treatment was followed by a rinse in deionized waterfor 5 minutes.

IR. cm⁻¹

˜970

˜1216

˜1667

˜2111

˜2140

˜3374

IBA

Carbon areal density 7×10¹⁵ atoms/cm²

Oxygen areal density 5.0×10¹⁵ atoms/cm²

Hydrogen areal density 4×10¹⁵ atoms/cm²

TM AFM

Smoothness=0.1 nms nm

Example 2 1:9 HF methanol 1′-five minute 5′ rinse in methanol

In this example, the passivation solution was 1:9 HF solution:methanol.After the pre-passivation steps were completed, the substrate(boron-doped, Si (100)) was immersed in the passivation solution for oneminute. This treatment was followed by a rinse in methanol for fiveminutes.

Data:

IR, cm⁻¹

˜970

˜1216

˜1448

˜1667

˜2111

˜2140

˜3374

IBA

Carbon areal density: 7×10¹⁵ atoms/cm²

Oxygen areal density: 5×10¹⁵ atoms/cm²

Hydrogen areal density: 4×10¹⁵ atoms/cm²

TMAFM

Smoothness=0.1 rms nm

Example 3 1:9 HF:2-propanol 1′-5′ rinse in DIH₂O

In this example the passivation solution was 1:9 HF solution: 2-propanol(isopropyl alcohol). After the pre-passivation steps were completed, thesubstrate (boron-doped Si(100) wafer) was immersed in the passivationsolution for one minute. This treatment was followed by a rinse indeionized water for 5 minutes.

Data:

IR, cm⁻¹

˜966

˜1044

˜1210

˜2111

˜2142

˜3391

IBA Carbon areal density: 6 × 10¹⁵ atoms/cm² Oxygen areal density: 5 ×10¹⁵ atoms/cm² Hydrogen areal density: 3 × 10¹⁵ atoms/cm²

TMAFM

Smoothness=0.1 rms nm

Example 4 1:9 HF:ethanol 1′-5′ rinse in DI H₂O

In this example the passivating solution was 1:9 HF solution: ethanol.After the pre-passivation steps were completed, the substrate(boron-doped Si(100) wafers) was immersed in the passivation solutionfor one minute. This treatment was followed by a rinse in deionizedwater for 5 minutes.

Data:

IR cm⁻¹

˜1035

˜1211

˜2111

˜2141

IBA Carbon areal density: 6 × 10¹⁵ atoms/cm² Oxygen areal density: 5 ×10¹⁵ atoms/cm² Hydrogen areal density: 3 × 10¹⁵ atoms/cm²

TMAFM

Smoothness=0.2 rms nm

Example 5 1:9 HF:ethanol 1-5 rinse in ethanol

In this example the passivating solution was 1:9 HF solution:ethanol.After the pre-passivation steps were completed, the substrate(boron-doped Si (100) wafers) immersed in the passivation solution for 5minutes. This treatment followed by a rinse in ethanol for 5 minutes.

Data:

˜1035

˜1211

˜2085

˜2111

˜2141

˜2856

˜2926

IBA

Carbon areal density:   6 × 10¹⁵ atoms/cm² Oxygen areal density: 4.6 ×10¹⁵ atoms/cm² Hydrogen areal density: 3.3 × 10¹⁵ atoms/cm²

TMAFM

Smoothness=0.1 rms nm

1-4 nm thick SiO₂ films were grown on passivated, ordered Si(100) inorder to correlate electrical properties and oxidation rates withSi(100) processing for ultrathin gate oxides. Ordered (1×1) Si(100)stable in ambient air is obtained at room temperature by wet chemicalcleaning [1]. The thickest oxides are grown by Rapid Thermal Oxidationor furnace oxidation at 1100° C., and the thinnest oxides are grown atroom temperature. These oxides are labeled here “ordered” because of theinitial ordering along SiO₂/Si(100).

Capacitance-Voltage and Current-Voltage measurements are generallyinconclusive for ultra-thin (1-2 nm) oxides because of leakage andbreakdown. But surface channel analysis (SCA), which measures theinterface charge, enables comparison between the “ordered” oxides andconventionally prepared oxides. When compared to a 3.2 nm thermal oxide,some of the “ordered” oxides exhibit a lower oxide charge density, and aminority carrier lifetime twice that measured for a conventionallyprepared thermal oxide. These electrical results appear to beindependent of whether ordering is detected beyond the interface or not,but is dependent on the initial Si(100) surface preparation andordering.

Thickness Qoxide Ts Cap. Leakage Å δ (μs) (Ff/μm2) (A/cm²⁾ Conventional32 8 e10 60 9 4 e-9 annealed Conventional 32 2 e11 475 9 4 e-9un-annealed JC2-4 23 4.12 e10 133 9.9 4.27 e-8 JC2-7 22 3.63 e10 125 9.88.55 e-8 JO11-4 26 6.43 e10 96 11.5 2.09 e-7

The reproducability of coverage using IBA on identical samples (not alldata included here) show that the process of the invention producesoxygen, hydrogen, and carbon coverages that are reproducible run to run.

Other experiments show that hydrogen coverage increases monotonically asthe immersion time in the passivation solution increases when thepassivation solution is methanol based. The areal density of oxygen forall samples shows sufficient oxygen to form at least a layer of SiO withsome areas of SiO₂. Obviously SiO must have another constituent to fillthe empty oxygen valence since the areal coverage indicates one oxygenper silicon atom. The most likely candidate is hydrogen, because it ispresent in a sufficient amount.

In all FTIR-IR experiments, 1:9 HF:alcohol was used. The absorptionfrequencies observed for the different SiH_(x) species correspond tomonohydrides at 2070-2090 cm⁻¹, dihydrides at 2090-2120 cm⁻¹, andtrihydrides at 2120-2150 cm⁻¹. Dihydrides and trihydrides were moreprominent at 2110 cm⁻¹ and 2140 cm⁻¹ respectively. Splitting of thedihydride peak was very apparent. SiO₂ was detected around 1215 cm⁻¹.The dihydride signal was the most prominent and most abundant SiH_(x)species detected for all HF:alcohol and aqueous HF solutions. Themonohydride was not present in all cases. The total amount of SiH_(x)species measured decreased with etching time in HF:alcohol, whereas, IBAshowed an increase in the net amount of hydrogen. Since IBA detects theabsolute coverage of hydrogen independent of its chemical state whileFTIR detection is sensitive to the bonding of the hydrogen, it can beconcluded that the increased amount of hydrogen does not bond to silicononly. The amount of oxide removed is lower for aqueous HF than forHF:alcohol also. In summary, FTIR correlates well with the IBAcompositional analysis which showed that the surface is terminated by atleast one continuous layer of SiO, and a discontinuous layer of SiO₂.The hydrogen bonds to the surface through SiOH bonds or through a morecomplex combination of Si and O atoms. Note that the FTIR shows O-Habsorption bands that point to the formation of SiOH as well.

FTIR Absorptions Species Absorption, cm⁻¹ SiH 2070-2090 SiH₂ 2090-2120SiH₃ 2120-2150 SiO₂ ˜1215

TMAFM images are scanned over an area of 2×2 μm². Surface roughness rmsvalues as given for a small particulate-free area. Surfaces treated in1:9 HF:alcohol followed by various rinses show similar rms values forsmoothness when compared to the reference aqueous HF (1:98 parts ofHF:H₂O) when followed by a water rinse. A value of 0.1 nm rms means thestandard deviation of atom height is 0.1 nm. In this process, thesmoothness can also be measured by counting the steps in the surface ona cross-section of that surface observed by high resolution TransmissionElectron Microscopy (See FIGS. 6A-B). Steps occur when a change in theplane of the atoms occurs. If one walked on the surface, a lack ofsmoothness would appear like a step of atoms. A perfectly flat surfacehas no steps. Typical surface preparations have one step per 10-20 Åwhile surfaces prepared per this invention have one step per 100-200 Åas seen in FIGS. A-B.

High resolution transmission electron microscopy shows increasedordering and/or a phase change for the dielectric layer as well. In thecase of Si(100) simply etched in HF:H₂O (2:98) FIG. 6A, the total amountof oxygen is 8.3±1.2×10¹⁵ oxygen atoms/cm² when averaged over threeidentically processed wafers. This value agrees with that determined byIBA. The oxide geometrical thickness as measured by High ResolutionTransmission Electron Microscopy (HRTEM) is 1.8 nm. For Si(100) etchedsolely in HF:methanol (1:9) such as in FIG. 6B, the O coverage is6.3±0.2×10¹⁵ oxygen/cm² when averaged over three identically processedwafers.

However, even though the oxygen content differs by 25%, the oxidegeometrical thickness measured by High Resolution Transmission ElectronMicroscopy (HRTEM) is also 1.8 nm. FIGS. 6A and 6B compare two HRTEMimages: FIG. 6A Si(100) simply etched in HF:H₂O (2:98) while FIG. 6Bdepicts si(100) etched solely in HF:methanol (1:9).

In FIGS. 6A and 6B, the SiO₂ layer 120 has formed as an oxide film onthe silicon layer 125. FIG. 6A shows that on average, all atoms in theoxide film appear displaced from lattice positions. However, in FIG. 6B,the SiO₂ films obtained after a modified RCA clean followed by etchingin HF:methanol (1:9) exhibit flat, periodic interfaces with si(100). Theoxide formed on Si(100) etched in HF:H₂O(2:98) exhibits more rippledinterfaces.

The 25% difference in areal density between the two films in FIGS. 6Aand 6B despite their fairly close geometrical thickness is a result ofthe volume expansion that accompanies oxygen insertion in Si(100). Thisvolume expansion can be accommodated partially by tetragonal strain,manifested normal to the (100) planes, and partially by periodic“rippling” in the (100) plans along the (100) interface. This datademonstrates that different interface phases of SiO₂ are formed by thismethod. The reduction in steps at the interface results in a decrease ininterface defect (defect) density as shown below.

The process described for producing a ultra-thin, low interface densitydefect layers forms an interface phase and for a dielectric materiallayer with a composition including at least silicon, oxygen andhydrogen. To a certain extent the exact composition and structure of thethin dielectric film thus formed is not necessarily ascertained (orascertainable). A fairly wide range of composition still yields a lowinterface defect density. The interface phase and/or film can becharacterized by data representing its physical characteristics or bythe process by which it is made.

From the foregoing, it appears that the following choices are mostefficacious in the practice of the process for forming the ultra-thindielectric layers of the invention: The degreasing step 21 uses a 10minute immersion in a degreasing solution kept at 80° C. The degreasingsolution is 4:1:1 H₂O:H₂O₂: NH₄OH. The substrate is rinsed, at step 31,in 18.3 megohm resistivity deionized water. The etching step 22 uses asolution of 98 parts water to 2 parts 49% HF solution. The immersiontime is two minutes. Again, at step 23, the substrate is rinsed afterthe etching step in 18.3 megohm deionized water. The primary oxidationstep 24 uses a 4:1:1 H₂O to H₂O₂:HCl solution. The substrate remainsimmersed in the solution for 10 minutes, and the solution is held at 80°C. At step 25, the substrate is rinsed in 18.3 megohm deionized water.The final step is the passivation step 26. The solution used is 1:9 HFsolution to methanol. The solution is used at room temperature. Thisstep is followed by a rinse 27 in methanol.

While the subject invention is described above in detail with referenceto various embodiments, it will be understood that changes andmodifications can be made to the described embodiments without departingfrom the spirit and scope of the invention as defined in the appendedclaims.

What is claimed is:
 1. A method of producing interface phase on asurface of a crystalline semiconductor substrate comprising the stepsof: a) etching the substrate surface until substantially all nativeoxide and at least several elemental or multi-elemental layers of bulksubstrate are removed; followed by: b) re-oxidizing the surface of thesubstrate; and c) after step (b) removing oxide formed on the surface instep (b) and passivating the surface to produce a resulting film thathas long-range ordering and a low interface defect density.
 2. Themethod of claim 1, wherein the interface phase has a thickness betweenabout one half and about ten nm.
 3. The method of claim 1, wherein afterstep (c) the substrate has one surface atomic step per 100 Å or morelinear distance.
 4. The method of claim 1, further comprising the stepof: a) immersing the substrate in a degreasing solution comprisingwater, an oxidizing agent, and a base; and thereafter b) rinsing thesubstrate, whereby the degreasing solution substantially completelyremoves organic contaminants from the substrate and the rinsing stepsubstantially completely removes the degreasing solution from thesubstrate.
 5. The method of claim 1, wherein etching comprises the stepsof: i) removing native oxide and initial elemental layers of thesubstrate by immersing the substrate in an etching solution, andsubsequently ii) rinsing the substrate.
 6. The method of claim 5,wherein the etching solution comprises hydrofluoric acid solution andwater.
 7. The method of claim 1, wherein step (c) comprises: i)immersing the substrate in an oxidizing solution comprising water, anoxidizing agent, and an acid; and subsequently ii) rinsing thesubstrate.
 8. The method of claim 7, wherein the oxidizing agent isselected from the group consisting of hydrogen peroxide, nitric acid,and hydrochloric acid.
 9. The method of claim 7, wherein the oxidizingsolution comprises water, hydrogen peroxide, and hydrochloric acid. 10.The method of claim 9, wherein the oxidizing solution comprises about 4parts water, about 1 part 25-40% hydrogen peroxide solution, and about 1part 25-40% concentrated hydrochloric acid, each component measured byvolume.
 11. The method of claim 1, wherein passivating comprises: i)immersing the substrate in a passivating solution comprising a solventand an etchant capable of dissolving any oxide on the surface of thesubstrate; and ii) rinsing the substrate to substantially remove theetchant.
 12. The method of claim 11, wherein rinsing further comprisesusing at least one of water, an alcoholic solvent or a non-alcoholicsolvent.
 13. The method of claim 11, wherein the solvent is at least oneof water, methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, and2-butanol.
 14. The method of claim 11, wherein the etchant is an acid.15. The method of claim 14, wherein the etchant is hydrofluoric acid.16. The method of claim 1, further comprising the step of oxidizing thesubstrate in a further final oxidation step.
 17. The method of claim 16,wherein the step of oxidizing the substrate in a further final oxidationstep comprises, increasing the thickness of material formed on thesubstrate surface from about 0.25 nm to about 100 nm.
 18. The method ofclaim 16, wherein the substrate is a semiconductor and the further finaloxidation step is a semiconductor oxidation process.
 19. The method ofclaim 1, wherein the substrate is a semiconductor material selected fromthe group consisting of Si, Si_(x)Ge_(1−x), GaAs, Si_(1−x−y)G_(x)C_(y),Si_(3(1−x))Ge_(3x)N_(4(1−δ)), Ge, Ga_(1−x)Al_(x)As,Si_(x)Ge_((1−x))(O_(y)N_(1−y))_(n),Si_(1−x−y)Ge_(x)C_(y)(O_(x)N_(1−z))_(n) and(Si_(1−x−y)Ge_(x)C_(y))₃N_(4−x−y).
 20. A method of producing ultra-thinfilms of interface phase material on a semiconductor substratecomprising: a) providing a semiconductor substrate; b) substantiallycompletely removing organic contaminants from a surface of thesubstrate; c) etching the substrate surface until substantially allnative oxide and at least several elemental or multi-elemental layers ofbulk substrate are removed; followed by: d) re-oxidizing the surface;and e) after step (d), removing oxide formed on the surface in step (d)and passivating the surface with a non-oxide passivation dielectriclayer.
 21. The method of claim 20, wherein step (a) comprises providinga crystalline semiconductor substrate.
 22. The method of claim 21,wherein step (b) comprises degreasing the surface.
 23. The method ofclaim 21, wherein step (e) comprises producing an ultra-thin layer ofdielectric on the surface, wherein the ultra-thin layer exhibitslong-range ordering.
 24. The method of claim 23, wherein producing anultra-thin layer comprises producing an interface phase material ofbetween about 0.5 and about 10 nm.
 25. The method of claim 24, furthercomprising the step of oxidizing the substrate in a final oxidation stepsubsequent to step (e).
 26. An ultra-thin film interface phase materialon a crystalline semiconductor substrate prepared by a processcomprising the steps of: a) degreasing a surface of the substrate; b)etching the surface until substantially all native oxide and at leastseveral elemental or multi-elemental layers of bulk substrate areremoved; followed by: c) re-oxidizing the surface of the substrate in aprimary oxidation step; and d) after step (c), removing oxide formed onthe surface in step (c) and passivating the surface to produce adielectric material layer that has long-range order and a low interfacedefect density.
 27. The material of claim 26, wherein the dielectricmaterial has a thickness substantially between about one-half and aboutten nm.
 28. The material of claim 26, wherein degreasing comprises: i)immersing the substrate in a degreasing solution comprising water, anoxidizing agent, and a base; and ii) rinsing the substrate, whereby thedegreasing solution substantially completely removes any organiccontaminants from the substrate and the rinsing step substantiallycompletely removes the degreasing solution from the substrate.
 29. Thematerial of claim 26, wherein etching the surface of the substratecomprises the steps of: i) removing native oxide and initial elementallayers of the substrate by immersing the substrate in an etchingsolution containing an etchant, and ii) rinsing the substrate.
 30. Thematerial of claim 26, wherein step (c) comprises: i) immersing thesubstrate in an oxidizing solution comprising water, an oxidizing agent,and an acid; and ii) rinsing the substrate in water.
 31. The material ofclaim 26, wherein the oxidizing agent is selected from the groupconsisting of hydrogen peroxide, nitric acid, and hydrochloric acid. 32.The material of claim 30, wherein the oxidizing solution compriseswater, hydrogen peroxide, and hydrochloric acid.
 33. The material ofclaim 32, wherein the oxidizing solution comprises about 4 parts water,about 1 part 25-40% hydrogen peroxide solution, and about 1 partconcentrated hydrochloric acid each component measured by volume. 34.The material of claim 26, wherein passivating comprises: i) immersingthe substrate in a passivating solution comprising a solvent and anetchant capable of dissolving any oxide on the surface of the substrate;and ii) rinsing the substrate to substantially remove the etchant. 35.The material of claim 34, wherein rinsing further comprises using atleast one of water, an alcoholic solvent and a non-alcoholic solvent.36. The material of claim 34, wherein the solvent is at least one ofwater, methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, and2-butanol.
 37. The material of claim 34, wherein the non-alcoholicsolvent of the passivating solution in claim 34 is at least one ofmethanol, ethanol, 1-propanol, 2-propanol, 1-butanol, and 2-butanol. 38.The material of claim 34, wherein the etchant is selected from the groupconsisting of hydrofluoric acid, H₂SO₄, and HNO₃.
 39. The material ofclaim 26, further comprising the step of oxidizing the substrate in afinal oxidation step subsequent to step (d).
 40. The material of claim39, wherein the step of oxidizing the substrate in a further finaloxidation step comprises, increasing the thickness of the film on thesubstrate surface from about 0.25 nm to about 100 nm.
 41. The materialof claim 39, wherein the substrate is a semiconductor and the furtherfinal oxidation step is a semiconductor oxidation process.
 42. Thematerial of claim 26, wherein the substrate is a semiconductor materialselected from the group consisting of Si, Si_(x)Ge_(1−x), GaAs,Si_(1−x−y)Ge_(x),C_(y), Si_(3(1−x))Ge_(3x)N_(4(1−δ)), Ge,Ga_(1−x)Al_(x)As, Si_(x)Ge_((1−x))(O_(y)N_(1−y))_(n),Si_(1−x−y)Ge_(x)C_(y)(O_(z)N_(1−z))_(n) and(Si_(1−X−y)Ge_(x)C_(y))₃N_(4−x−y).
 43. A semiconductor device includinga dielectric interface phase material prepared by a process comprisingthe steps of: a) degreasing the surface of a crystalline semiconductorsubstrate; b) etching a substrate surface until substantially all nativeoxide and at least several elemental or multi-elemental layers of bulksubstrate are removed; followed by: c) re-oxidizing the surface of thesubstrate in a primary oxidation step; and d) after step (c), removingoxide formed on the surface in step (c) and passivating the surface ofthe substrate to produce a dielectric material layer that has a lowinterface defect density and long-range ordering.
 44. The semiconductordevice of claim 43, wherein the device is a MOS device, and thedielectric material forms a dielectric layer separating a gate from thesemiconductor substrate.
 45. The semiconductor device of claim 43,wherein the resulting dielectric material is between about one-half andabout ten nm.
 46. The semiconductor device of claim 43, wherein etchingcomprises the steps of: i) removing native oxide and initial elementallayers of the substrate by immersing the substrate in an etchingsolution containing an etchant; and ii) rinsing the substrate withwater.
 47. The semiconductor device of claim 43, wherein step (c)comprises: i) immersing the substrate in an oxidizing solutioncomprising water, an oxidizing agent, and an acid; and ii) rinsing thesubstrate.
 48. The semiconductor device of claim 47, wherein theoxidizing agent is selected from the group consisting of hydrogenperoxide, nitric acid, and sulfuric acid.
 49. The semiconductor deviceof claim 47, wherein the oxidizing solution comprises water, hydrogenperoxide, and hydrochloric acid.
 50. The semiconductor device of claim49, wherein the oxidizing solution comprises about 4 parts water, about1 part 25-40% hydrogen peroxide solution, and about 1 part concentratedhydrochloric acid.
 51. The semiconductor device of claim 43, wherein thepassivating step comprises: i) immersing the substrate in a passivatingsolution comprising a solvent and an etchant capable of dissolving anyoxide on the surface of the substrate; and ii) rinsing the substrate tosubstantially remove the etchant.
 52. The semiconductor device of claim51, wherein rinsing further comprises using at least one of water, analcoholic solvent or a non-alcoholic solvent.
 53. The semiconductordevice of claim 51, wherein the solvent is at least one of water,methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, and 2-butanol. 54.The semiconductor device of claim 51, wherein the etchant ishydrofluoric acid:methanol (1:9).
 55. The semiconductor device of claim43, further comprising the step of oxidizing the substrate in a finaloxidation step subsequent to step (d).
 56. The semiconductor device ofclaim 55, wherein the step of oxidizing the substrate in a finaloxidation step comprises, increasing the thickness of the dielectricfilm on the substrate surface from about 0.25 nm to about 100 nm. 57.The semiconductor device of claim 55, wherein the substrate is asemiconductor and the final oxidation step is a semiconductor oxidationprocess.
 58. The semiconductor device of claim 43, wherein the substrateis a semiconductor material selected from the group consisting of Si,Si_(x)Ge_(1−x), GaAs, Si_(1−x−y)Ge_(x)C_(y),Si_(3(1−x))Ge_(3x)N_(4(1−δ)), Ge, Ga_(1−x)Al_(x)As,Si_(x)Ge_((1−x))(O_(y)N_(1−y))_(n),Si_(1−x−y)Ge_(x)C_(y)(O_(z)N_(1−z))_(n) and(Si_(1−x−y)Ge_(x)C_(y))₃N_(4−x−y).
 59. An ultra-thin film dielectricmaterial comprising silicon, oxygen, and hydrogen, wherein the surfaceof the material has one surface atomic step per 100 Å or more.
 60. Theultra-thin film dielectric material of claim 59, wherein the dielectricmaterial has FTIR absorptions of: cm⁻¹ 950-1100 1190-1225 2105-21202139-2145.
 61. The ultra-thin film dielectric material of claim 59,wherein the dielectric material has FTIR absorptions of: cm³¹ ¹ 950-11001190-1225 2105-2120 2139-2145 2850-2860 2910-2935.
 62. The ultra-thinfilm dielectric material of claim 59, wherein the film is from about0.25 to about 100 nm thick.
 63. The ultra-thin film dielectric materialof claim 59, wherein the dielectric material has a capacitance ofsubstantially between 9.5 to 12 femtoFarads/square micrometer for a filmwith a thickness substantially between 22 and 26 angstroms.
 64. Theultra-thin film dielectric of claim 59, wherein the dielectric has a lowflat-band voltage.
 65. The ultra-thin film dielectric of claim 64,wherein the dielectric has a flat-band voltage of less than about 0.65Volts for a 20 angstrom thick film.
 66. A semiconductor device having adielectric layer comprising an ordered oxide of a semiconductor materialchosen from the group consisting of Si, Si_(x)Ge_(1−x), GaAs,Si_(1−x−y)Ge_(x)C_(y), Si_(3(1−x))Ge_(3x)N_(4(1−δ)), Ge,Ga_(1−x)Al_(x)As,Si_(x)Ge_((1−x))(O_(y)N_(1−y))_(n)Si_(1−x−y)Ge_(x)C_(y)(O_(z)N_(1−z))_(n)and (Si_(1−x−y)Ge_(x)C_(y))₃N_(4−x−y), with long-range ordering and anordered interface phase of oxygen and hydrogen all on an atomic polishedsurface of a substrate of the semiconductor material.
 67. The device ofclaim 66, wherein the oxide layer comprises an oxidized surface layer ofthe substrate of the semiconductor material.
 68. The device of claim 67,wherein the oxide layer is ultra thin.
 69. The device of claim 68,wherein the oxide layer is substantially about 0.5 to 20 nm.
 70. Thedevice of claim 69, wherein the interface phase has long-range order andis less than 10 monolayers thick.
 71. A composition of matter comprisingan ultra-thin interface phase on a crystalline semiconductor surface,the interface phase exhibiting long range ordering.
 72. The compositionof matter of claim 71, further comprising a layer of oxide of the samesemiconductor which is a semiconductor selected from the groupconsisting of Si, Si_(x)Ge_(1−x), GaAs, Si_(1−x−y)Ge_(x)C_(y),Si_(3(1−x))Ge_(3x)N_(4(1−δ)), Ge, Ga_(1−x)Al_(x)As,Si_(x)Ge_((1−x))(O_(y)N_(1−y))_(n),Si_(1−x−y)Ge_(x)C_(y)(O_(z)N_(1−z))_(n) and(Si_(1−x−y)Ge_(x)C_(y))₃N_(4−x−y).
 73. A method of producing anatomically smooth crystalline semiconductor substrate surface comprisingthe steps of: a) degreasing the surface of the substrate; b) etching thesubstrate surface until substantially all native oxide and at leastseveral elemental or multi-elemental layers of bulk substrate areremoved; followed by: c) re-oxidizing the surface of the substrate; andd) after step (c), removing the oxide formed on the surface in step (c)and passivating the surface to produce a surface that has about onesurface atomic step per 100 Å or more linear distance.
 74. A method ofproducing an interface phase on a surface of a crystalline semiconductorsubstrate comprising the steps of: a) degreasing the surface of thesubstrate; b) etching the substrate surface until substantially allnative oxide and at least several elemental or multi-elemental layers ofbulk substrate are removed; followed by: c) re-oxidizing the surface ofthe substrate; and d) after step (c) removing the oxide formed on thesurface in step (c) and passivating the surface by lowering the chemicalreactivity of the surface to a reagent, thereby slowing the rate ofsurface reaction to the reagent; and e) reacting the reagent with thesemiconductor at the surface thus treated to form ordered andcommensurate layers of a product of the reaction having low flat-bandvoltage, charge carrier lifetime greater than 60 microseconds, and highcapacitance.
 75. A semiconductor device having a dielectric layercomprising long-range ordered oxidized semiconductor material on anatomically polished substrate of that semiconductor material with asmoothness characterized by one surface atomic step for 100 Å or greaterlinear distance, wherein the semiconductor material is chosen from thegroup consisting of Si, Si_(x)Ge_(1−x), GaAs, Si_(1−x−y)Ge_(x)C_(y),Si₃₍ _(1−x))Ge_(3x)N_(4(1−δ)), Ge, Ga_(1−x)Al_(x)As,Si_(x)Ge_((1−x))(O_(y)N_(1−y))_(n),Si_(1−x−y)Ge_(x)C_(y)(O_(z)N_(1−z))_(n) and(Si_(1−x−y)Ge_(x)C_(y))₃N_(4−x−y).
 76. The method of claim 1, whereinthe interface phase material is an ultra-thin film of dielectricmaterial.
 77. The material of claim 26, wherein a final oxidation stepin the process of its preparation form an ordered oxide material. 78.The semiconductor device of claim 55, wherein the final oxidizing stepproduces a thin dielectric oxide material having long-range orderingwhere closest to the substrate surface.
 79. A composition of matterprepared on a surface of a crystalline semiconductor substrate by amethod comprising the steps of: a) degreasing the surface of thesubstrate; b) etching a substrate surface until substantially all nativeoxide and at least several elemental or multi-elemental layers of bulksubstrate are removed; followed by: c) chemically re-oxidizing thesurface of the substrate; and d) after step (c), removing oxide formedon the surface in step (c) and passivating the surface to produce aresulting film that has long-range ordering and a low interface defectdensity.
 80. The composition of matter prepared by the method steps ofclaim 79, wherein degreasing comprises the steps of: i) immersing thesubstrate in a degreasing solution comprising water, an oxidizing agent,and a base; and ii) rinsing the substrate, whereby the degreasingsolution substantially completely removes organic contaminants from thesubstrate and the rinsing step substantially completely removes thedegreasing solution from the substrate.
 81. The composition of matterprepared by the method steps of claim 79, wherein etching comprises thesteps of: i) removing native oxide and initial elemental layers of thesubstrate by immersing the substrate in an etching solution, containingan etchant, and ii) rinsing the substrate.
 82. The composition of matterprepared by the method steps of claim 79, wherein step (c) comprises: i)immersing the substrate in an oxidizing solution comprising water, anoxidizing agent, and an acid; and ii) rinsing the substrate in water.83. The composition of matter prepared by the method steps of claim 82,wherein the oxidizing agent is selected from the group consisting ofhydrogen peroxide, nitric acid, and hydrochloric acid.
 84. Thecomposition of matter prepared by the method steps of claim 82, whereinthe oxidizing solution comprises water, hydrogen peroxide, andhydrochloric acid.
 85. The composition of matter prepared by the methodsteps of claim 79, wherein step (d) comprises: i) immersing thesubstrate in a passivating solution comprising a solvent and an etchantcapable of dissolving any oxide on the surface of the substrate; and ii)rinsing the substrate to substantially remove the etchant.
 86. Thecomposition of matter prepared by the method steps of claim 85, whereinrinsing further comprises rinsing with at least one of water, analcoholic solvent or a non-alcoholic solvent.
 87. The composition ofmatter prepared by the method steps of claim 85, wherein the solvent isat least one of water, methanol, ethanol, 1-propanol, 2-propanol,1-butanol, and 2-butanol.
 88. The composition of matter prepared by themethod steps of claim 85, wherein the etchant is an acid.
 89. Thecomposition of matter prepared by the method steps of claim 88, whereinthe etchant is hydrofluoric acid.
 90. The composition of matter preparedby the method steps of claim 79, further comprising the step ofoxidizing the substrate in a further final oxidation step.
 91. Thecomposition of matter prepared by the method steps of claim 90, whereinthe step of oxidizing the substrate in a further final oxidation stepcomprises increasing the thickness of an interface phase material on thesubstrate surface from about 0.25 nm to about 100 nm.
 92. Thecomposition of matter prepared by the method steps of claim 90, whereinthe substrate is a semiconductor and the further final oxidation step isa semiconductor oxidation process.
 93. The composition of matterprepared by the method steps of claim 92, wherein the substrate is asemiconductor material selected from the group consisting of Si,Si_(x)Ge_(1−x), GaAs, Si_(1−x−y)Ge_(x)C_(y),Si_(3(1−x))Ge_(3x)N_(4(1−δ)), Ge, Ga_(1−x)Al_(x)As,Si_(x)Ge_((1−x))(O_(y)N_(1−y))_(n),Si_(1−x−y)Ge_(x)C_(y)(O_(z)N_(1−z))_(n) and(Si_(1−x−y)Ge_(x)C_(y))₃N_(4−x−y).
 94. The method of claim 11, whereinsaid etchant is HF:methanol (1:9).
 95. The method of claim 11, whereinsaid substrate is Si(100).
 96. The semiconductor device of claim 43,wherein the substrate is the semiconductor material Si(100).
 97. Amethod of producing a planar dielectric layer on a planar semiconductorsubstrate comprising: a) providing a crystalline semiconductor substratehaving a polished surface; b) after step (a), degreasing the surfacewith a degreasing agent that is oxidizing and strongly basic to removecontaminants from the surface including organic impurities; c) afterstep (b), etching the surface with an acid solution to remove nativeoxide and ionized impurities imbedded in native oxide on the surface orlocated on the surface; d) after step (c), re-oxidizing the surface withan oxidizing agent to create a chemically grown oxide layer on thesurface and to trap in the oxide layer any impurity left on the surface;and e) after step (d), using a solvent and an etchant in solution,passivating the surface to remove the oxide of step (d) and to grow along-range ordered passivation layer on the surface.
 98. The methodaccording to claim 97, wherein step (a) comprises providing acrystalline semiconductor wafer.
 99. The method according to claim 98,wherein the etchant of step (e) comprises HF, and the passivation layergrown is comprised of oxygen and hydrogen.
 100. The method according toclaim 99, wherein the passivation layer grown in step (e) is less thanfive monolayers of oxygen and hydrogen atoms ordered to conform to anordered atomic crystal structure of the semiconductor at said surface.101. The method according to claim 100, wherein the semiconductor issilicon.
 102. The method according to claim 101, wherein the silicon isSi(100).
 103. The method according to claim 97, further comprising thesteps of rinsing the surface after each of steps (b), (c), (d) and (e).104. The method according to claim 103, wherein the step of rinsingafter step (e) comprises rinsing in methanol.
 105. The method accordingto claim 97, further comprising: f) growing an ordered oxide layer onthe surface on top of the passivating layer.
 106. The method accordingto claim 97, wherein the oxidizing agent of step (d) comprises H₂O, H₂O₂and HCl.
 107. The method according to claim 102, further comprisinggrowing a layer of ordered SiO₂ on the surface on top of the passivationlayer.
 108. The method according to claim 102, wherein the passivationlayer of step (e) is comprised of oxygen and hydrogen.
 109. The methodaccording to claim 108, wherein the passivation layer grown in step (e)is less than five monolayers of oxygen and hydrogen atoms ordered toconform to an ordered atomic crystal structure of the silicon at saidsurface.